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| ? semiconductor components industries, llc, 2014 august, 2014 ? rev. 3 1 publication order number: ncp6915/d ncp6915 6 channels pmic with one dcdc converter and 5 ldos the ncp6915 integrated circuit is part of the on semiconductor mini power management ic family. it is optimized to supply battery powered portable application sub?systems such as camera function, microprocessors ... etc. this device integrates one high efficiency 600 ma step?down dcdc converter with dvs (dynamic voltage scaling) and 5 low dropout (ldo) voltage regulators in wlcsp16 package. features ? one dcdc converter: ? peak efficiency 96% ? programmable output voltage from 0.8 v to 2.3 v by 50 mv steps ? 600 ma output current capability ? five low noise ? low dropout regulators ? programmable output voltage from 1.7 v to 3.3 v for ldos 1,2,3 ? programmable output voltage from 1.2 v to 2.85 v for ldo 4 & 5 ? 200 ma output current capability: ldo?s 1,2,3 & 4 ? 300 ma output current capability: ldo 5 ? 45 vrms low output noise ? control ? 400 khz / 3.4 mhz i 2 c control interface ? hardware enable pin ? customizable power up sequencer ? extended input voltage range 2.5 v to 5.5 v ? support of newest battery technologies ? optimized power efficiency ? 82 a very low quiescent current at no load ? dynamic voltage scaling on dcdc converter ? regulators can be supplied from dcdc converter output ? small footprint ? package wlcsp16 1.56 x 1.56 mm 2 ? dcdc converter runs at 3.0 mhz using a 1 h inductor and 10 f capacitor or 2.2 h inductor and 4.7 f capacitor ? this is a pb?free device typical applications ? cellular phones ? digital cameras ? personal digital assistant and portable media player ? gps wlcsp16 case 567gf marking diagram* http://onsemi.com see detailed ordering and shipping information on page 23 o f this data sheet. ordering information a b c d 123 4 vout2 vin1 agnd vout3 vout1 scl vbg vout4 fb hwen sda vin2 pvin sw pgnd vout5 (top view) a = assembly location l = wafer lot y = year ww = work week = pb?free package 6915a alyww *pb?free indicator, ?g? or microdot ? ?, may or may not be present.
ncp6915 http://onsemi.com 2 enabling system supply dcdc1 out 2.2uf 10 uf 1uh 1.0 uf ncp6915 fb pvin sw pgnd power up/ down sequencer thermal protection sda scl hwen dcdc1 600 ma 100 nf core agnd vbg vin1 vin2 1uf system supply system supply or dcdc out vout1 ldo1 200 ma 1.0 uf vout2 ldo2 200 ma 1.0 uf vout3 ldo3 200 ma 1.0 uf vout4 ldo4 200 ma 1.0 uf vout5 ldo5 300 ma 1uf figure 1. functional block diagram processor i 2 c i 2 c ncp6915 http://onsemi.com 3 table 1. pin out description pin name type description power b1 vin1 power input analog supply. this pin is the device analog, digital and ldo 1, 2 & 3 supply. a 1.0 f ceramic capacitor or larger must bypass this input to ground. this capacitor should be placed as close a possible to this pin. c2 vbg analog input reference voltage. a 0.1 f ceramic capacitor must bypass this pin to the ground c1 agnd analog ground analog ground. analog and digital modules ground. must be connected to the system ground. control and serial interface b3 hwen digital input hardware enable. active high will enable the part; there is internal pull down resistor on this pin. b2 scl digital input i 2 c interface clock c3 sda digital input/output i 2 c interface data dcdc converter a4 pvin power input dcdc power supply. this pin must be decoupled to ground by a 2.2 f ceramic capacitor. this capacitor should be placed as close a possible to this pin. b4 sw power output dcdc switch power pin connects power transistors to one end of the inductor. typical application uses 1.0 h inductor; refer to application section for more information. a3 fb analog input dcdc feedback voltage. must be connected to the output capacitor. this is the input to the error amplifier. c4 pgnd power ground dcdc power ground. this pin is the power ground and carries the high switching current. high quality ground must be provided to prevent noise spikes. to avoid high?density current flow in a limited pcb track, a local ground plane is recommended. ldo regulators b1 vin1 power input ldo 1,2 & 3 power and core supply (see power table) d3 vin2 power input ldo 4&5 power supply this pin requires a 1 f decoupling capacitor. a2 vout1 power output ldo 1 output power. this pin requires a 1 f decoupling capacitor. a1 vout2 power output ldo 2 output power. this pin requires a 1 f decoupling capacitor. d1 vout3 power output ldo 3 output power. this pin requires a 1 f decoupling capacitor. d2 vout4 power output ldo 4 output power. this pin requires a 1 f decoupling capacitor. d4 vout5 power output ldo 5 output power. this pin requires a 1 f decoupling capacitor. table 2. maximum ratings rating symbol value unit analog and power pins: avin, pvin, sw, vin1, vin2, vout1, vout2, vout3, vout4, vout5, fb, vbg pins v a ?0.3 to +6.0 v digital pins: scl, sda, hwen pin: input voltage input current v dg i dg ?0.3 to v a +0.3 6.0 10 v ma storage temperature range t stg ?65 to + 150 c maximum junction temperature t jmax ?40 to +150 c moisture sensitivity (note 1) msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a. ncp6915 http://onsemi.com 4 table 3. recommended operating conditions symbol parameter conditions min typ max unit v in1 pv in core power supply, dcdc power supply and ldos 1, 2 & 3 2.5 5.5 v v in2 ldos 4 & 5 input voltage range 1.7 5.5 v t a ambient temperature range ?40 25 +85 c t j junction temperature range (note 3) ?40 25 +125 c r ja thermal resistance junction to case ? 80 ? c/w p d power dissipation rating (note 5) t a = 25 c ? 1250 ? mw t a = 85 c ? 500 ? mw l inductor for dcdc converter (note 2) 1 2.2 h co output capacitor for dcdc converter (note 2) 10 f output capacitors for ldo (note 2) 0.65 1 f c bg output capacitors for v bg 100 nf cpvin input capacitor for dcdc converter (note 2) 2.2 f cvin1 input capacitor for vin1 (note 2) 1 f cvin2 input capacitor for vin2 (note 2) 1 f functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 2. refer to the application information section of this data sheet for more details. 3. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 4. the r ca is dependent of the pcb heat dissipation. board used to drive this data was a 2? x 2? ncpxxxevb board. it is a multilayer boar d with 1?once internal power and ground planes and 2?once copper traces on top and bottom of the board. 5. the maximum power dissipation (p d ) is dependent by input voltage, maximum output current and external components selected. r ca 125 t a p d r jc with r ja r jc r ca table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. pvin = v in1 = v in2 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2 v, ldo1, 2 & 4= 2.8 v, ldo 3 & 5 = 1.8 v, typical values are referenced to t j = + 25 c and default configuration (note 7). symbol parameter conditions min typ max unit supply current: pins vin1, vin2, pvin i q operating quiescent current dcdc on ? no load ? no switching ldos off t a = up to +85 c ? 32 ? a dcdc on ? no load ? no switching ldos on ? no load t a = up to +85 c ? 82 ? dcdc off ldos on ? no load t a = up to +85 c ? 65 ? i sleep product sleep mode current hwen on all dcdc and ldos off v in = 2.5 v to 5.5 v t a = up to +85 c ? 7 ? a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 7. refer to the application information section of this data sheet for more details. 8. guaranteed by design and characterized. ncp6915 http://onsemi.com 5 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. pvin = v in1 = v in2 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2 v, ldo1, 2 & 4= 2.8 v, ldo 3 & 5 = 1.8 v, typical values are referenced to t j = + 25 c and default configuration (note 7). symbol unit max typ min conditions parameter supply current: pins vin1, vin2, pvin i off product off current hwen off i 2 c interface disabled v in = 2.5 v to 5.5 v t a = up to +85 c ? 0.3 ? a dcdc converter pv in input voltage range 2.5 ? 5.5 v i outmax maximum output current (note 8) 0.6 ? ? a vout output voltage dc error io = 300 ma, pwm mode ?1.5 0 1.5 % dc out dcdc output voltage programmable 50 mv steps (note 8) 0.8 2.3 v f sw switching frequency 2.7 3 3.3 mhz i pk peak inductor current open loop 2.5 v pv in 5.5 v 1.0 1.3 1.6 a load regulation i out from 300 ma to i outmax ? ?0.5 ? %/a line regulation i out = 300 ma 2.5 v v in 5.5 v ? 0 ? %/v d maximum duty cycle ? 100 ? % t start soft?start time time from i 2 c command ack to 90% of output voltage, vout = 1.2 v. ? 128 s r disdcdc dcdc active output discharge ? 8 ? ldo1, ldo2, ldo3 v in1 ldo1, ldo2, ldo3 input voltage range 2.5 ? 5.5 v i outmax1,2, 3 maximum output current 200 ? ? ma i sc1,2, 3 short circuit protection ? 500 ma foldback current 130 ma v out1, 2, 3 output voltage programmable, see table. (note 8) 1.7 3.3 v t start1 soft?start time time from i 2 c command ack to 90% of output voltage. ? 128 s v out1,2, 3 output voltage accuracy dc i out1,2, 3 = 150 ma ?2 v nom +2 % load regulation i out1,2, 3 = 0 ma to 200 ma ? 0.4 ? % line regulation v in1 = (vout + drop) to 5.5 v v out1,2 = 2.8 v, v out3 = 1.8 v i out1,2,3 = 200 ma ? 0.3 ? % v drop dropout voltage i out1,2,3 = 200 ma, v out = 3.3 v ? 2% 160 mv i out1,23 = 200 ma, v out = 2.8 v ? 2% ? 185 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 7. refer to the application information section of this data sheet for more details. 8. guaranteed by design and characterized. ncp6915 http://onsemi.com 6 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. pvin = v in1 = v in2 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2 v, ldo1, 2 & 4= 2.8 v, ldo 3 & 5 = 1.8 v, typical values are referenced to t j = + 25 c and default configuration (note 7). symbol unit max typ min conditions parameter ldo1, ldo2, ldo3 psrr ripple rejection f = 1 khz, 100 mv peak to peak v out1,2 = 2.8 v, v out3 = 1.8 v i out1,2,3 = 5 ma ? ?70 ? db f = 10 khz, 100 mv peak to peak v out1,2 = 2.8 v, v out3 = 1.8 v i out1,2,3 = 5 ma ? ?60 ? noise 10 hz 100 khz, 5 ma v out1,2,3 = 2.8 v ? 45 ? v r disldo1,2, 3 ldo active output discharge ? 25 ? ldo4 and ldo5 v in2 ldo4 and ldo5 input voltage 1.7 ? 5.5 v i outmax4 maximum output current 200 ? ? ma i outmax5 maximum output current 300 ? ? ma i sc4 short circuit protection ? 500 ? ma i sc5 short circuit protection ? 600 ? ma i sc4 foldback protection 130 ? ma i sc5 foldback protection 190 ? ma v out4,5 ldo 4&5 output voltage programmable, see table. (note 8) 1.2 ? 2.85 v t start2 soft?start time time from i 2 c command ack to 90% of output voltage. ? 128 s v out4 output voltage accuracy i out4 = 200 ma ?2 v nom +2 % v out5 output voltage accuracy i out5 = 300 ma ?2 v nom +2 % load regulation i out4 = 0 ma to 200 ma i out5 = 0 ma to 300 ma ? 0.4 ? % line regulation v in2 = (vout + drop) to 5.5 v v out4 = 2.8 v, v out5 = 1.8 v i out4 = 200 ma, i out5 = 300 ma ? 0.3 ? % v drop dropout voltage i out4,5 = 200 ma v out4,5 = 2.8 v ? 2% ? 165 mv i out5 = 300 ma v out5 = 1.8 v ? 2% 290 psrr ripple rejection f = 1 khz, 100 mv peak to peak i out4= 5 ma, i out5 = 5 ma ? ?70 ? db f = 10 khz, 100 mv peak to peak i out4,5 = 5 ma ? ?60 ? noise 10 hz 100 khz, 5 ma v out4,5 = 2.8 v ? 45 ? v r disldo4,5 ldo 4&5 active output discharge ? 25 ? hwen v ih high level input voltage threshold 1.1 ? ? v v il low level voltage threshold ? ? 0.4 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 7. refer to the application information section of this data sheet for more details. 8. guaranteed by design and characterized. ncp6915 http://onsemi.com 7 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. pvin = v in1 = v in2 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2 v, ldo1, 2 & 4= 2.8 v, ldo 3 & 5 = 1.8 v, typical values are referenced to t j = + 25 c and default configuration (note 7). symbol unit max typ min conditions parameter hwen i en 0.1 1 a i 2 c v i2c voltage at scl and sda line 1.7 ? 5.0 v v i2cil scl, sda low input voltage scl, sda pin (note 6) ? ? 0.5 v v i2cih scl, sda high input voltage scl, sda pin (note 6) 0.8 x v i2 cc ? ? v v i2col scl, sda low output voltage i sink = 3 ma (note 8) ? ? 0.4 v f scl i 2 c clock frequency (note 8) ? ? 3.4 mhz total device v uvlo under voltage lockout v in falling ? ? 2.3 v v uvloh under voltage lockout hysteresis v in rising 60 ? 200 mv t sd thermal shut down protection ? 150 ? c t warning warning rising edge ? 135 ? c t sdr thermal shut down rearming ? 110 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 7. refer to the application information section of this data sheet for more details. 8. guaranteed by design and characterized. ncp6915 http://onsemi.com 8 detailed description the ncp6915 is optimized to supply the different sub systems of battery powered portable applications. the ic can be supplied directly from the latest technology single cell batteries such as lithium?polymer as well as from triple alkaline cells. alternatively, the ic can be supplied from a pre?regulated supply rail in case of multi?cell or mains powered applications. the output voltage range, current capabilities and performance of the switched mode dcdc converter are well suited to supply the different peripherals in the system as well as to supply processor cores. to reduce overall power consumption of the application, dynamic voltage scaling (dvs) is supported on the dcdc converter. for pwm operation, the converter runs on a local 3 mhz clock. a low power pfm mode is provided that ensures that even at low loads high efficiency can be obtained. all the switching components are integrated including the compensation networks and synchronous rectifier. small sized 1 uh inductor and 10 uf bypass capacitor are required for typical applications. the general purpose low dropout regulators can be used to supply the lower power rails in the application. to improve on overall application standby current, the bias current of these regulators are made very low. the regulators have two separated input supply pin to be able to connect them independently to either the system supply voltage or to the output of the dcdc converter in the application. the regulators are bypassed with a small size 1.0 uf capacitor. the ic is controlled through the i 2 c interface that allows to program amongst others the output voltages of the different supply rails as well as to configure its behavior. in addition to this bus, a digital hardware enable control pin (hwen) is provided. under voltage lockout the core does not operate for voltages below the under voltage lockout (uvlo) threshold and all internal circuitry, both analog and digital, is held in reset. ncp6915 functionality is guaranteed down to v uvlo when the battery is falling. a hysteresis is implemented to avoid erratic on / off behavior of the ic. due to its 200 mv hysteresis, when the battery is rising, re?start is guaranteed at 2.5 v. thermal shutdown given the output power capabilities of the on chip step down converters and low drop out regulators the thermal capabilities of the device can be exceeded. a thermal protection circuit is therefore implemented to prevent the part from damage. this protection circuit is only activated when the core is in active mode (at least one output channel is enabled). during thermal shutdown, all outputs of ncp6915 are off. when ncp6915 returns from thermal shutdown, it can re?start in two different configurations depending on rearm[7:6] bits ($09 register ) . if rearm[7:6] = 00 then ncp6915 re?starts with default register values, otherwise it re?starts with register values set prior to thermal shutdown. in addition, a thermal warning is implemented which can inform the processor through an interrupt that ncp6915 is close to its thermal shutdown so that preventive action can be taken by software. active output discharge by default, to prevent any disturbances on power?up sequence, output dischar ge is activated as soon as the input voltage is valid (upper than uvlo+ hyst). after power up sequence and during on state, output discharge can be independently enabled / disabled by appropriate settings in the dis register (refer to the register definition section). if a power down sequence, uvlo or thermal shutdown events occur, the output discharge paths are activated until the next pus and on state. when the ic is turned off when vin1 drops down below uvlo threshold, no shut down sequence is expected, all supplies are disabled and outputs turn to high impedance. enabling the hwen pin controls the device start up. if hwen is raised, this starts the power up sequencer (pus). if hwen is made low, device enters in shutdown mode and all regulators will be turned off with inverted pus of power up. a built?in pull?down resistor disables the device if this pin is left unconnected. when hwen is high, the different power rails can be independently enabled / disabled by writing the appropriate bit in the enable register. power up sequence and hwen when enabling part with hwen pin, the part will be set with the default configuration factory programmed in the registers, if no i 2 c programming has been done as described in the below table. ncp6915 http://onsemi.com 9 table 5. default power up sequencer delay (in s) from tstart sequence default assignment default vprog default mode and on/off 128 to: 000 dcdc 1.20 v auto pfm/pwm off 256 t1: 001 ldo1 2.80 v off 512 t2: 011 ldo2 2.80 v off 640 t3: 100 ldo3 1.80 v off 768 t4: 101 ldo4 2.80 v off 896 t5: 110 ldo5 1.80 v off note: additional power sequence are available. please contact your on semiconductor representative for further information. figure 2. ipus the initial power up sequence (ipus) is described in figure 2. remark 1: t2 ? t1 = 2x 128 s in the default configuration. can be reprogrammed at 128 s by i 2 c. remark 2: ldos must be turned on sequentially to avoid inrush current on v in source. so it?s strongly recommended to turn them one by one, even if the default pus sequence is changed by i 2 c. o f f m o d e por uvlo hwen (dcdc_t[2:0] + 1) x 128 s * dvs ramp time 600 us typ vin1, vin2 vout dcdc soft start 90% bias time (ldox_t[2:0] + 1) x 128 s * vout ldox 128 us i c figure 3. ipus in order to power up the circuit, the input voltage vin1 has to rise above the vuvlo threshold. this triggers the internal core circuitry power up including: internal references core circuitry ?wake up time? dcdc ?bias time? these delays are internals and cannot be bypassed. ncp6915 http://onsemi.com 10 as the default configuration factory is programmed with disable state for the dcdc and ldos, an i 2 c access must be done at the end of the bias time to enable the supplies. in addition a user programmable delay will also take place between end of core circuitry turn on (bias time) and start up time: the powersupplies_t [2..0] bits of time register will set this user programmable delay with a 128 s resolution (note: please contact your on semiconductor representative for additional resolution options). the output discharge of the dcdc and ldos are done during this time slot. note: during the bias time, the i 2 c interface is not active during the first 50 s. any i 2 c request to the ic during this time period will result in a nack reply. however, i 2 c registers can be read and written while hwen pin is still low (except blanking time of 50 s typical). by programming the appropriate registers (see registers description section), the power up sequence default can be modified and set upon requirements (please contact your on representative for additional pus options) o f f m o d e por uvlo hwen (dcdc _t[2:0] + 1) x 128 s * dvs ramp time 70 us typ vin1, vin2 vout dcdc soft start 90% bias time (ldox_t[2:0] + 1) x 128 s * vout ldox 128 us i c s l e e p m o d e 600 s min figure 4. sleep mode pus (smpus) a third turn on sequence is also available by i 2 c. indeed each power supply can be turn off/on through i 2 c register. in this case no biasing time is required except for dcdc bias time (32 s typical). por uvlo hwen dvs ramp time vin1, vin2 vout dcdc soft start 90% vout ldox 128 us i c ldox, dcdc off/ on bias time 32 s figure 5. on mode pus (opus) shutdown by hwen when hwen is tied low, all supplies are disabled with reverted turn on sequence detailed in default power up sequencer table. if different turn off sequence is required, a different programming can be done by i 2 c. dcdc converter the converter can operate in two modes: pwm mode and pfm mode. in pwm mode the converter operates at a fixed frequency and adapts its duty cycle to regulate to the desired output voltage. the advantage of this mode is that the emi noise is predictable. however, at lower loadings the efficiency is degraded. in pfm mode some switching pulses are skipped to control the output voltage. this allows maintaining high efficiency even at low loadings. in addition, no high frequency clock is required which provides additional current savings. the switchover point between both modes is chosen depending on the supply conditions such that highest efficiency is obtained over the entire load range. the switch over between pwm/pfm modes can occur automatically but the switcher can be set in auto switching mode pfm / pwm by i 2 c programming. a soft start is provided to limit inrush currents when enabling the converters. the soft start consists of ramping gradually the reference to the switcher. additional current limitation is provided by a peak current limiter that monitors and limits the current through the inductor. dcdc converter output voltage can be set by i 2 c modedcdc bit is used to program switcher mode control ncp6915 http://onsemi.com 11 table 6. modedcdc bit description modedcdc dcdc mode control 0 mode is auto switching pfm / pwm (default) 1 mode is pwm only dynamic voltage scaling (dvs) step down converters support dynamic voltage scaling (dvs). this means the output v oltage can be reprogrammed based upon i 2 c commands to provide the different voltages required by the processor. the change between set points is managed in a smooth manner without disturbing the operation of the processor. when programming a higher voltage, the reference of the switcher and therefore the output is raised in 50 mv/ 2.67 s (default) steps such that the dv/dt is controlled. when programming a lower voltage the output voltage will decrease based on the output capacitor value and the load. the dvs system makes sure that the voltage ramp down will not exceed the steps settings. v2 internal reference output voltage t v figure 6. dynamic voltage scaling effect timing programmability dcdc converter has two different output voltages programmed by default in the dcdc_v1 and v2 bank. the dcdc output voltage can be changed from v1 to v2 with the dcdc_v2/v1 bit in $08 register. table 7. dcdc_v2/1 bit description dcdc_v2/1 bit description 0 output voltage is set to dcdc_v2 1 output voltage is set to dcdc_v1(default) the two dvs bits in register time determine ramp up time per each voltage step. table 8. dvs bit description dvs [0] bit description 0 2.67 s per step (default) 1 10.67 s per step dcdc step down converter and ldos end of turn on sequence to indicate the end of the power up sequence, a power good sense bit is available at the $0a address. (sen_pg). sense bit is set to 0 during power up sequence and 16 x digital clock (128 s by default). the power good sense bit is released to 1 after this sequence and trig ack_pg interrupt. the interrupt is reset by a read or hwen. figure 7. power good behavior interrupt the interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected (dual edge monitoring). the interrupt sources include: table 9. interrupt sources register $0b uvlo under voltage threshold pus end of power up sequence wnrg thermal warning tsd thermal shutdown individual bits generating interrupts will be set to 1 in the int_ack register (i 2 c read only register), indicating the interrupt source. int_ack register is reset by an i 2 c read. int_sen registers (read only registers) are real time indicators of interrupt sources. force register reset the i 2 c registers are reset when the part is in off mode: ? vin ncp6915 http://onsemi.com 13 typical operating characteristics figure 14. ldo4 psrr 0 100 1m 100k 10k 1k frequency (hz) psrr (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 v in = 5 v v in = 3.6 v v in = 1.7 v 10k 0.1 100k 10k 1k 100 frequency (hz) noise (nv/ hz ) figure 15. ldo1 output noise versus frequency and vout, vin 3.6 v 1k 100 10 10 1 v out = 1.8 v v out = 2.8 v ncp6915 http://onsemi.com 14 i 2 c compatible interface ncp6915 can support a subset of i 2 c protocol, below are detailed introduction for i 2 c programming. i 2 c communication description on semiconductor communication protocol is a subset of i 2 c protocol. figure 16. general protocol description the first byte transmitted is the chip address (with lsb bit sets to 1 for a read operation, or sets to 0 for a write operation). then the following data will be: ? in case of a write operation, the register address (@reg) we want to write in followed by the data we will write in the chip. the writing process is incremental. so the first data will be written in @reg, the second one in @reg + 1 .... the data are optional. ? in case of read operation, the ncp6915 will output the data out from the last register that has been accessed by the last write operation. like writing process, reading process is an incremental process. read out from part the master will first make a ?pseudo write? transaction with no data to set the internal address register. then, a stop then start or a repeated start will initiate the read transaction from the register address the initial write transaction has set: figure 17. read out from part the first write sequence will set the internal pointer on the register we want access to. then the read transaction will start at the address the write transaction has initiated. ncp6915 http://onsemi.com 15 transaction with real write then read 1. with stop then start figure 18. write followed by read transaction write in part write operation will be achieved by only one transaction. after chip address, the mcu first data will be the internal register we want access to, then following data will be the data we want to write in reg, reg + 1, reg + 2, ...., reg +n. write n registers: figure 19. write in n registers i 2 c address ncp6915 has fixed i 2 c but dif ferent i 2 c address (by default $10, 7 bit address, see below table a7~a1), ncp6915 supports 7?bit address only. table 10. ncp6915 i 2 c address i 2 c address hex a7 a6 a5 a4 a3 a2 a1 a0 add0 (default) w $20 /r $21 0 0 1 0 0 0 0 x address $10 0 0 1 0 0 0 0 ? different default address is available upon request ncp6915 http://onsemi.com 16 register map following register map describes i 2 c registers. registers can be: r read only register rc read then clear rw read and write register rwm read, write and can be modified by the ic reserved address is reserved and register is not physically designed spare address is reserved and register is physically designed table 11. registers summary address register name type default function $00 general_settings rw $00 dvs control settings $01 ldo1_settings rw $39 ldo1 register settings $02 ldo2_settings rw $79 ldo2 register settings $03 ldo3_settings rw $8c ldo3 register settings $04 ldo4_settings rw $be ldo4 register settings $05 ldo5_settings rw $d1 ldo5 register settings $06 dcdc_settings1 rw $15 dcdc register settings 1 $07 dcdc_settings2 rw $13 dcdc register settings 2 $08 enable rw $80 enable and dvs register settings $09 pulldown rw $3f active discharge and rearming register $0a status r $04 status or sense register $0b interrupt_ack rc $00 interrupt register $0c to $ff ? ? ? reserved. do not access to those registers details of the registers are in the following section. registers description table 12. general_settings register name: general_settings address: $00 type: rw default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare = 0 dvs spare = 0 spare = 0 spare = 0 spare = 0 table 13. bit description of general_settings register bit bit description dvs[0] ramp up time per voltage step table 14. ldo1_settings register name: ldo1_settings address: $01 type: rw default: $39 d7 d6 d5 d4 d3 d2 d1 d0 ldo1_t [2:0] ldo1_v[4:0] ncp6915 http://onsemi.com 17 table 15. bit description of ldo1_settings register bit bit description ldo1_v[4:0] ldo1 output voltage setting, refer to table 16 ldo1_t[2:0] ldo1 startup delay time setting (delay time between hwen transitions from low to high and ldo1 startup delay time = (ldo1_t[2:0] + 1) * 128 s remark: it?s not recommended to use same ldox_t for two consecutives ldos. 64 s, 128 s, 1 ms, 2 ms otp options (128 s default value) table 16. ldo2_settings register name: ldo2_settings address: $02 type: rw default: $79 d7 d6 d5 d4 d3 d2 d1 d0 ldo2_t [2:0] ldo2_v[4:0] table 17. bit description of ldo2_settings register bit bit description ldo2_v[4:0] ldo2 output voltage setting, refer to table 16 ldo2_t[2:0] ldo2 startup delay time setting (delay time between hwen transitions from low to high and ldo2 startup delay time = (ldo2_t[2:0] + 1) * 128 s remark: it?s not recommended to use same ldox_t for two consecutives ldos. table 18. ldo3_settings register name: ldo3_settings address: $03 type: rw default: $8c d7 d6 d5 d4 d3 d2 d1 d0 ldo3_t [2:0] ldo3_v[4:0] table 19. bit description of ldo3_settings register bit bit description ldo3_v[4:0] ldo3 output voltage setting, refer to table 16 ldo3_t[2:0] ldo3 startup delay time setting (delay time between hwen transitions from low to high and ldo3 startup delay time = (ldo3_t[2:0] + 1) * 128 s remark: it?s not recommended to use same ldox_t for two consecutives ldos. table 20. ldo1_v[4:0], ldo2_v[4:0], ldo3_v[4:0] setting table register vout (v) register vout (v) register vout (v) register vout (v) 00000 1.70 01000 1.70 10000 2.10 11000 2.75 00001 1.70 01001 1.70 10001 2.20 11001 2.80 00010 1.70 01010 1.70 10010 2.30 11010 2.85 00011 1.70 01011 1.75 10011 2.40 11011 2.90 00100 1.70 01100 1.80 10100 2.50 11100 2.95 00101 1.70 01101 1.85 10101 2.60 11101 3.00 00110 1.70 01110 1.90 10110 2.65 11110 3.10 00111 1.70 01111 2.00 10111 2.70 11111 3.30 ncp6915 http://onsemi.com 18 table 21. ldo4_settings register name: ldo4_settings address: $04 type: rw default: $be d7 d6 d5 d4 d3 d2 d1 d0 ldo4_t [2:0] ldo4_v[4:0] table 22. bit description of ldo4_settings register bit bit description ldo4_v[4:0] ldo4 output voltage setting, refer to table 21 ldo4_t[2:0] ldo4 startup delay time setting (delay time between hwen transitions from low to high and ldo4 startup delay time = (ldo4_t[2:0] + 1) * 128 s remark: it?s not recommended to use same ldox_t for two consecutives ldos. table 23. ldo5_settings register name: ldo5_settings address: $05 type: rw default: $d1 d7 d6 d5 d4 d3 d2 d1 d0 ldo5_t [2:0] ldo5_v[4:0] table 24. bit description of ldo5_settings register bit bit description ldo5_v[4:0] ldo5 output voltage setting, refer to table 21 ldo5_t[2:0] ldo5 startup delay time setting (delay time between hwen transitions from low to high and ldo5 startup delay time = (ldo5_t[2:0] + 1) * 128 s remark: it?s not recommended to use same ldox_t for two consecutives ldos. table 25. ldo4_v[4:0], ldo5_v[4:0] setting table register vout (v) register vout (v) register vout (v) register vout (v) 00000 1.20 01000 1.35 10000 1.75 11000 2.40 00001 1.20 01001 1.40 10001 1.80 11001 2.50 00010 1.20 01010 1.45 10010 1.85 11010 2.60 00011 1.20 01011 1.50 10011 1.90 11011 2.65 00100 1.20 01100 1.55 10100 2.00 11100 2.70 00101 1.20 01101 1.60 10101 2.10 11101 2.75 00110 1.25 01110 1.65 10110 2.20 11110 2.80 00111 1.30 01111 1.70 10111 2.30 11111 2.85 table 26. dcdc_settings1 register name: dcdc_settings1 address: $06 type: rw default: $15 d7 d6 d5 d4 d3 d2 d1 d0 dcdc_t[2:0] dcdc_v1[4:0] ncp6915 http://onsemi.com 19 table 27. bit description of dcdc_settings1 register bit bit description dcdc_v1[4:0] dcdc output voltage setting 1, refer to table 25 dcdc_t[2:0] dcdc startup delay time setting (delay time between hwen transitions from low to high and dcdc startup delay time = (dcdc_t[2:0] + 1) * 128 s table 28. dcdc_settings2 register name: dcdc_settings2 address: $07 type: rw default: $13 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 modedcdc dcdc_v2[4:0] table 29. bit description of dcdc_settings2 register bit bit description dcdc_v2[4:0] dcdc output voltage setting 2, refer to table 25 modedcdc dcdc operating mode 0: auto switching pfm / pwm (default) 1: forced pwm table 30. dcdc_vx[4:0] setting table dcdc_v1/2 vout (v) dcdc_v1/2 vout (v) dcdc_v1/2 vout (v) dcdc_v1/2 vout (v) 00000 0.80 v 01000 1.15 v 10000 1.55 v 11000 1.95 v 00001 0.80 v 01001 (v1)* 1.20 v 10001 1.60 v 11001 2.00 v 00010 0.85 v 01010 1.25 v 10010 1.65 v 11010 2.05 v 00011 0.90 v 01011 1.30 v 10011 1.70 v 11011 2.10 v 00100 0.95 v 01100 1.35 v 10100 1.75 v 11100 2.15 v 00101 1.00 v 01101 1.40 v 10101 1.80 v 11101 2.20 v 00110 1.05 v 01110 1.45 v 10110 1.85 v 11110 2.25 v 00111 (v2) 1.10 v 01111 1.50 v 10111 1.90 v 11111 2.30 v *default value: v1 table 31. enable register name: enable address: $08 type: rw default: $80 d7 d6 d5 d4 d3 d2 d1 d0 dcdc_v2/v1 spare = 0 dcdc_ en ldo5_ en ldo4_ en ldo3_ en ldo2_ en ldo1_ en table 32. bit description of enable register bit bit description dcdc_v2/v1 dcdc output voltage setting 0: dcdc converter output voltage is set to dcdc_v2 1: dcdc converter output voltage is set to dcdc_v1 dcdc_ en dcdc enabling 0: disabled 1: enabled ncp6915 http://onsemi.com 20 table 32. bit description of enable register bit bit description ldo5_ en ldo5 enabling 0: disabled 1: enabled ldo4_ en ldo4 enabling 0: disabled 1: enabled ldo3_ en ldo3 enabling 0: disabled 1: enabled ldo2_ en ldo2 enabling 0: disabled 1: enabled ldo1_ en ldo1 enabling 0: disabled 1: enabled table 33. pulldown register name: pulldown address: $09 type: rw default: $3f d7 d6 d5 d4 d3 d2 d1 d0 rearm_ tsd[7] rearm_ tsd[6] dcdc_ pulldown ldo5_ pulldown ldo4_ pulldown ldo3_ pulldown ldo2_ pulldown ldo1_ pulldown table 34. bit description of pulldown register bit bit description rearm_ tsd[7:6] device rearming after thermal shut down 11: n/a 10: no re?arming after tsd 0 1: re-arming active after tsd with no reset of i 2 c registers: new power-up sequence is initiated with i 2 c registers values. 00 : re-arming active after tsd with reset of i 2 c registers: new power-up sequence is initiated with default i 2 c registers values (default). dcdc_ pulldown dcdc active output discharge 0: disabled 1: enabled ldo5_ pulldown ldo5 active output discharge 0: disabled 1: enabled ldo4_ pulldown ldo4 active output discharge 0: disabled 1: enabled ldo3_ pulldown ldo3 active output discharge 0: disabled 1: enabled ldo2_ pulldown ldo2 active output discharge 0: disabled 1: enabled ldo1_ pulldown ldo1 active output discharge 0: disabled 1: enabled ncp6915 http://onsemi.com 21 table 35. status register name: status address: $0a type: r default: $04 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare = 0 spare = 0 sen_uvlo sen_/pus sen_tsd sen_wnrg table 36. bit description of status register bit bit description sen_uvlo uvlo sense 0: input voltage is higher than (uvlo + hyst) threshold. 1: input voltage is lower than (uvlo) threshold. sen_pus power up sequence 0: power up sequence on going 1: power up sequence finished or hwen is low sen_tsd thermal shut down sense 0: ic temperature is below tsd threshold 1: ic temperature is over tsd threshold sen_wnrg thermal warning sense 0: ic temperature is below thermal warning threshold 1: ic temperature is over thermal warning threshold table 37. interrupt_ack register name: interrupt_ack address: $0b type: rc default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare = 0 spare = 0 ack_uvlo ack_pus ack_tsd ack_wnrg table 38. bit description of interrupt_ack register bit bit description ack_uvlo uvlo sense acknowledge 0: cleared 1: sen_uvlo dual edge triggered interrupt ack_pus power up sequence sense acknowledge 0: cleared 1: sen_pus rising edge triggered interrupt ack_tsd thermal shut down sense acknowledge 0: cleared 1: sen_tsd dual edge triggered interrupt ack_wnrg thermal warning sense acknowledge 0: cleared 1: sen_wnrg dual edge triggered interrupt note: sen_pus rising edge appears (16 ) x 128 s (default) after hwen rising edge. ncp6915 http://onsemi.com 22 demoboard informations figure 20. demoboard schematic components selection inductor selection the inductance of the inductor is determined by given peak?to?peak ripple current i l_pp of approximately 20% to 50% of the maximum output current i out_max for a trade?off between transient response and output ripple. the inductance corresponding to the given current ripple is: l v in v out v out v in f sw i l_pp the selected inductor must have high enough saturation current rating to be higher than the maximum peak current that is i l_max i out_max i l_pp 2 the inductor also needs to have high enough current rating based on temperature rise concern. low dcr is good for efficiency improvement and temperature rise reduction. table 39 shows recommended. ncp6915 http://onsemi.com 23 table 39. inductor selection supplier part value ( h) size (mm) dc rated current (a) dcr max at 25 c (m ) toko dfe201610r-h-1r0n 1 2.0x1.6 mm 2.2 48 toko mdt2012-clr1r0am 1 2.0x1.2 mm 2.15 80 murata lqm21pn1r0ngr 1 2.0x1.2 mm 1.3 66 murata lqm2mpn1r0ng0 1 2.0x1.6 mm 1.4 85 cyntec pife2016t-1r0 1 2.0x1.6 mm 2 80 table 40. board components description quantity reference schem part description part number manufacturer 1 b1 header200 4 sl 5.08/4/90b weidmuller 1 b2 header200_12 2.54 mm, 77313-101-06lf fc 3 c1,c3,c5 100uf grm31cr60j107me39# murata 2 c7,c8 2.2uf grm188r60j225ke19# murata 2 c9,c11 10uf grm188r60j106me47# murata 1 c10 100nf grm033c801j104ke84b murata 5 c12,c13,c14,c15,c16 1uf grm155r70j105ka12# murata 2 gnd2,gnd gnd jumper d3082f05 harvin 1 j1 con26a n2526-5002rb 3m 1 l1 1uh dfe201610r-h-1r0n toko 1 q3 nmos bss138lt1 on semiconductor 1 q4 nmos ntd4969nt4g on semiconductor 2 r1,r2 50 ohms fc0603e50r0btbst1 vishay 4 s1,s2,s3,s11 strap 2pins 77311-401-36lf fci 1 tp2 hwen 77311-401-36lf fci 1 s12 logic_supply 77311-401-36lf fci 1 tp1 vbat 77311-401-36lf fci 1 tp3 sda 77311-401-36lf fci 1 tp4 scl 77311-401-36lf fci 1 tp5 vin1 77311-401-36lf fci 1 tp6 vin2 77311-401-36lf fci 1 tp7 dcdc_vout 77311-401-36lf fci 1 tp8 vout1 77311-401-36lf fci 1 tp9 vout2 77311-401-36lf fci 1 tp10 vout3 77311-401-36lf fci 1 tp11 vout4 77311-401-36lf fci 1 tp12 vout5 77311-401-36lf fci 1 tp13 fb1 77311-401-36lf fci 1 tp14 smb4 77311-401-36lf fci 1 tp15 smb3 77311-401-36lf fci 1 u1 pmic ncp6915 on semiconductor ordering information device marking package shipping ? NCP6915AFCCLT1G 6915a wlcsp 1.56x1.56 mm (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncp6915 http://onsemi.com 24 package dimensions wlcsp16, 1.56x1.56 case 567gf issue d seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 1.56 bsc e b 0.24 0.29 e 0.40 bsc 0.60 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 16x b 4 c b a 0.10 c a a1 a2 c 0.17 0.23 1.56 bsc 0.25 16x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.10 c 2x top view side view bottom view note 3 e recommended package outline 123 pitch d pitch a1 a2 0.33 0.39 detail a e/2 e/2 a3 detail a a2 a3 0.04 bsc on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp6915/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative |
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